About Me

Hello there! I am Dr. Sagnik Nath, Assistant Teaching Professor in the Department of Computer Science and Engineering at the University of California, Santa Cruz. My academic home is Baskin Engineering, and since Fall 2020, I have been immersed in teaching, mentoring, and designing inclusive computing education experiences that reflect both technical sophistication and equity-focused pedagogy.

Before UCSC, during my Ph.D. in Electrical Engineering at Rensselaer Polytechnic Institute (graduated May 2020), I worked on developing automatic placement and routing methodologies for asynchronous Single Flux Quantum (SFQ) circuit designs. My earlier research includes optimizing SFQ circuits using EDA tools like Cadence Innovus and conducting timing characterization of SFQ cell libraries. 

My journey in engineering began with a B.E. in Electronics and Telecommunication Engineering from the Indian Institute of Engineering Science and Technology, Shibpur, in 2015.

At UCSC, I teach courses such as CSE 12, CSE 100, CSE 120, CSE 122, and CSE 222A, where I blend topics like computer architecture, VLSI design, and inclusive teaching strategies to close equity gaps in engineering education. I amm passionate about developing pedagogical approaches that support students from diverse backgrounds, especially community college learners, in their journey to transfer and succeed in computing disciplines.

Alongside teaching and domain research, I am also deeply involved in engineering education research. I serve as an Associate Program Chair for SIGCSE TS (2025 and 2026), and I’ve reviewed for conferences like ASEE, FIE, and SIGCSE, in addition to participating on National Science Foundation (NSF) panels for proposal reviews across different programs. I am also a member of the Computing Alliance of Hispanic-Serving Institutions (CAHSI) and I contributed to the 2024 Broadening Participation in AI report, an initiative focused on equity-driven AI education.

I am also a member of the UCSC Hardware Systems Collective (HSC), a multidisciplinary research group within the CSE department dedicated to advancing the design, architecture, programming, and integration of next-generation hardware systems. 

I also recently lead a fully online summer program that introduces pre-transfer community college students to core data science concepts through interactive notebooks and lectures. The goal is to build self-efficacy, reduce math anxiety, and make data science feel more approachable and empowering. It’s been one of the most fulfilling parts of my work.

I believe in research-based teaching, mentorship through ownership, and using computing to solve human problems, not just technical ones. Many of my undergraduate mentees have explored AI model benchmarking, transformer architectures, or even built civic tech prototypes in collaboration with the California DMV and ORA Systems. Watching them grow into confident, curious thinkers is why I do what I do.

I am active on LinkedIn and always open to connecting, discussing ideas, or exploring potential collaborations.

Academic & Professional Journey

• Ph.D., Electrical Engineering, Rensselaer Polytechnic Institute, New York, USA (2020)
  Focused on SFQ circuit design methodologies and automation: circuits that use superconducting logic for high-speed computing

• B.E., Electronics & Telecommunication Engineering, IIEST Shibpur, India (2015)
  
  

Research Highlights & Teaching Focus

My scholarship includes work on:

• Small Language Models (SLMs) & AI-Augmented Instruction : I am currently exploring how Small Language Models can be embedded into Raspberry Pi or Arduino-driven robotics platforms to enable semi-autonomous behavior and lightweight natural language interaction. This research serves as a bridge between low-level embedded systems and higher-level AI reasoning, offering students a pathway to learn control systems, inference, and real-time decision-making through affordable, intelligent hardware.

• Automatic Placement & Routing for Asynchronous SFQ Circuits : As part of my Ph.D. research, I developed an automated methodology for placing and routing asynchronous Single Flux Quantum (SFQ) circuits using passive transmission lines and Cadence Innovus, a commercial EDA tool. I designed a set of dual-rail asynchronous SFQ cells and wrote conversion scripts to transform single-rail netlists synthesized from behavioral Verilog into compatible dual-rail structures. This enabled successful layout generation that passed both layout vs. schematic (LVS) and design rule checks (DRC). I also implemented a back-annotation process where post-layout transmission line lengths were reintegrated into analog simulations to validate timing behavior. The methodology was demonstrated using a custom-designed 4-bit arithmetic logic unit.
  
  

• Timing Characterization of SFQ Cell Libraries : To support scalable verification of superconducting circuits, I also worked on developing timing models for rapid SFQ logic cells. This involved extracting propagation delays and minimum pulse spacing values at multiple process and operating corners using Monte Carlo simulations. I modeled these behaviors in Verilog to enable timing back annotation and static timing analysis, eliminating the need for costly full-transient simulations at the Josephson junction level. My analysis accounted for complex delay dependencies arising from inter-cell interactions, state-dependent behavior, and current redistribution effects. A parallel counter design served as the reference circuit to validate the methodology, showing close agreement with full SPICE-level simulations.

What Drives Me

I am driven by the aim to blend technical rigor with inclusive pedagogy, making computing education both challenging and accessible. Whether it's guiding students through VLSI concepts, enabling their transition from community colleges, or weaving thoughtful instructional design into large courses, I seek teaching that empowers all learners to claim their place in computing.